Originally, solid state cameras utilized CCD imaging arrays. However, improvements in CMOS based cameras have made CMOS imaging arrays the imaging array of choice for many applications. In CMOS imaging arrays each pixel in the image is created by a corresponding photodiode that measures the light intensity of the image at a corresponding point in the image. The charge is measured by a readout circuit that includes a floating diffusion node that acts as a capacitor on which the accumulated charge can be transferred. Initially, the floating diffusion node is charged to a fixed reset potential. The charge is then transferred to the floating diffusion node which causes the potential on the floating diffusion node to decrease. The potential on the floating diffusion node is then readout and converted to the light intensity value corresponding to that pixel. Variations in the reset potential due to noise introduced by the switching of the floating diffusion node to the reset potential result in the introduction of noise into the light intensity measurement, as the potential is no longer “fixed” at a precisely known value.
To reduce the noise introduced by the reset noise, a technique referred to as correlated double sampling is used. In correlated double sampling, the potential of the floating diffusion node after the floating diffusion node has been reset, but before the charge is transferred from the photodiode is measured and stored in a sample and hold circuit. The charge from the photodiode is then transferred to the floating diffusion node and the potential of the floating diffusion node is measured again. The potential value stored in the sample and hold circuit is then subtracted from the measured potential to arrive at a signal indicative of the amount of charge that was accumulated on the photodiode during the exposure. This technique greatly reduces the problems introduced by variations in the reset potential.
While correlated double sampling reduces the problems associated with variations in the reset potential on the floating diffusion node, the sample and hold circuit introduces a new source of noise into the measurements. The sample and hold circuit typically includes a switch that gates the voltage to be sampled onto a capacitor. When the switch opens after having connected the capacitor to the voltage source, noise from the switch opening alters the voltage on the capacitor by an amount that is proportional to √{square root over (KT/C)}, where C is the capacitance of the storage capacitor in the sample and hold circuit. In principle, this noise can be reduced by using a large capacitor; however, there is a limit to the size of capacitor that can be provided that is imposed by the available circuit area in the imaging array chip. Hence, a sample and hold circuit that introduces less noise while having a size that is less than or equal to that of the single capacitor is needed.